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Physical Implementation engineer with experience of full synthesis to GDS flow.
- at least 4 years experience in IC design
- self-motivated
- good communication skills and able to work well in a small team
- able to contribute to defining a new 90nm physical implementation
methodology for high speed processor and SoC design.
- able to define and lead TA activity on a large SoC design
including multiple in-house designed processor cores as well as
externally sourced IP
- previous experience of chip level TA work essential, preferably using Synopsys Primetime
- flexible to move between all physical design activities as required
- experience of 0.13um circuit level design techniques essential
- familiar with crosstalk timing and signal integrity issues
- knowledge of 90nm design flows and methods would be an advantage
- Knowledge of Magma physical design tools, Perl & TCL scripting would be useful
Description : Working in a design centre of ~30 people on leading edge DSL CO chips
including high-speed processor design, new IP core creation and
integration of the world's leading IP. Main duties will be
contribution to 90nm physical implementation methodology and chip-level
TA of large SoC's. Reporting to the physical build team leader. The
candidate will have the opportunity to own all aspects of IP core
implementation including TA, chip-level integration, logical and
physical synthesis, crosstalk and signal integrity analysis, P&R, etc.
There will also be the occasional opportunity to extend experience into
front-end work.
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